1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a method for fabricating a nanowire transistor (NWT).
2. Description of the Related Art
Gate straps are often used in the fabrication of nanowire transistor (NWT) architectures to provide a means for contacting the outer shell electrode (e.g., TaAIN or WN outer shell) for core-shell-shell (CSS) nanostructures, or to provide a gate material for core-shell (CS) nanostructures. Due to the fact that the gate-strap material must have a low resistivity, a conductive material such as metal or an in-situ doped a-Si material is deposited.
FIG. 1 is a cross-sectional view depicting the conductive material that remains following an anisotropic etching (prior art). In either of the CSS or CS devices, there is concern regarding any conductive material that remains following the standard gate etch step. This conductive material remains due to the fact that the conductive layer is deposited with a highly conformal deposition process (e.g., CVD or ALD) that fully surrounds the CSS nanowires, and is then etched using an anisotropic plasma etch. Due to the cylindrical shape of the nanostructures, the conductive material remains along the edges of the wires where it is shadowed from the plasma etch process (i.e., at the reentrant corners along the lower/southern hemicylinder of the wires). These reentrant regions, when filled with conductive material, create “stringers” that may inadvertently connect the gate to either the source or the drain. Since these “stringers” can short the device, it is crucial that they be removed.
It would be advantageous if NW transistors could be formed without conductive reentrant stringers that can inadvertently short the gate electrode to either the drain or source electrodes.